module top_module ();
    
    reg clk,reset,t;
    wire q;

    tff my_tff(
        .clk(clk),
        .reset(reset),
        .t(t),
        .q(q)
    );
    
    always @(posedge clk) begin
        if(reset) t <= 1'b0;
        else t <= 1'b1;
    end
    
    initial begin
        reset = 1'b0;
        #10 reset = 1'b1;
        #10 reset = 1'b0;
    end
    
    initial begin
        clk = 1'b0;
    end
    
    always begin
        #5 clk = ~clk;
    end
    
endmodule
